The phase lock loop is commonly used in digital circuitry to synchronize clock signals. Its application includes, for example, anything requiring clock synchronization or clock synthesis, such as radar applications and telecommunications. Continuing advances in technology have resulted in an increase in the operating speed of electrical devices. Unfortunately, the speed of lock detectors in the phase lock loop has not increased at a pace sufficient to keep up with technology.
Current lock detectors incorporate multiple logic devices that cause significant logic delays. These delays limit the maximum operating frequency of current lock detectors. One technique to incorporate these frequency limited lock detectors in higher frequency circuitry reduces the clock signal frequency prior to presentation to the lock detector. This results in increased overhead due to additional elements placed in the phase lock loop, and introduces more error sources and potential for device failure.